last person to reply WINS

[Odin's eyes]

if State 0 defines a high assertion to the tri-state buffer, and state 1 defines a low assertion to the tri-state buffer, can state 2 define both high and low assertions to the tristate buffer if it de-multiplexed after passing through an inverter gate?

No, State 2 tells you that this is way too complicated to solve based on your descriptions.

[uknesvuinng]

I'm sticking with 42.

[Dr Weir]

I'm sticking with just winning.

[TechnoWraith]

but winning requires that state 2 be asserted high to allows the PGL package logic to return a non-zero value to the inverter gate.

[uknesvuinng]

I'm sticking with just winning.

I think you're better at losing. You've done it more times than any of us.

[TechnoWraith]

But winning is even better.

[uknesvuinng]

Yeah, I like winning too.

[TechnoWraith]

too bad you're not right now.

[Odin's eyes]

I've figured out that the problem with your question TechnoWraith is the inverted gate.
Really, do you have to invert it? A normal gate works just fine and inverting it just seems a bit... showy?

[uknesvuinng]

Electronics geeks

[Dr Weir]

I think you're better at losing. You've done it more times than any of us.

But I've won even more times.

[uknesvuinng]

Number of posts = numbers of times you've lost.

[TechnoWraith]

Number of posts = the number of times you've won!

[srg]

But I've won even more times.

I care not

[Eoin]

Orbit with xylitol for healthier teeth